Xilinx ISE ver 8.2.02i is optimizing away and removing "redundant" logic - help!

james7uw · 2006-09-09T18:39:19+00:00

Hello All,I am writing a VHDL design for a Xilinx FPGA usingISE ver 8.2.02i (8.2 SP 2) and I'm trying to getpost-map simulating correctly now that I havepost-translate simulating correctly. I put "keep"attributes on every single signal, including thosein the ports (editor keystroke macros help a lot).I also ran the following command line in a command(DOS) window: (just run the following three linestogether with spaces at the line breaks; it is acopy from the DOS window): Note the added -u totry to prevent logic removal, which is why I hadto run this in the command window; it's notavailable as a setting in map properties.map.exe -ise -intstyle ise -p xc4vfx12-ff668-10 -cm speed-detail-pr b -k 4 -c 100 -u -o user_logic.pcfI have the map optimization now set for speed inmy project, reflected in this command. I triedsetting "no optimization" as well as all the otheroptimization choices. The above command made thepost map files for me. Now, at least all the redis gone from Post-Map simulation and some of thebytes are right in my first section of output. Ithink this is due to all the "keep" attributes Iadded. My removed "redundant logic" list was madea little smaller. Here is the syntax for "keep": signal mysignal : std_logic; -- declare a signal attribute keep : string; -- you just need this once -- then you can do the next line for each signal you want. attribute keep of mysignal : signal is "true"; -- this goes in the architecture section after the signaldeclarations and -- before the "begin".(Thanks to the thread "Looking for ways to keepdiagnostic signal from being optimized out(Xilinx)" here in This syntax is found in the Constraints Guide,cgd.pdf.Here is a partial list of the removed logic:Section 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND XST_GNDVCC XST_VCCRedundant Block(s):TYPE BLOCKLOCALBUF u0/my_sub_mod_128_0_xo1/LUT3_D_BUFLOCALBUF ...

Sep 09, 2006 41 Replies

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james7uw 19 years ago

Thanks for the extra info, guys. Am now stuck on a ModelSim path problem that has a plain user (me) stuck dead in his tracks. I am starting a new thread for that.

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Weng Tianxiang 19 years ago

Hi David, I never said what I have listed is the best one in performance, but it really saves me a lot.

I never pay attention to what has already been built in Xilinx ISE. I never spend time doing unnecessary things.

What I pay most of my attention to is to write right logic that runs fastest in the market!

Thank you, Xilinx engieers, who provide a really reliable platform to let me do my best and make my money and my living.

Thank you.

Weng

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