I had a question in regards to the Xilinx ISE. I have a design in which i use synopsys for synthesis. Then, I import the edif file into XILINX ISE. Next, I go to "Create Timing Constraints."
What i find here is a list of values that the Xilinx ISE assumes to be clocks. The problem is, these values do not contain some of the clock signals. Why is this? Is there a way i can force it to put some of my signals in this clock constraint section?
It has a lot of signals in this section that aren't even clock signals, is there a way to define this section better?
synopsys for synthesis. Then, I import the edif file into XILINX ISE. Next, I go to "Create Timing Constraints."
The problem is, these values do not contain some of the clock signals. Why is this? Is there a way i can force it to put some of my signals in this clock constraint section?
there a way to define this section better?
Hi Xavier, the Xilinx ISE constraints editor usually relates signals as clocks if they are connected to the clock input of a FF/register/counter.. sometimes when you code your design (i assume that you are using HDL) you connect signals such as FF outputs to a FF clock input (intetionaly or not) when you do so the constraints editor infers that you meant for a clock and add it to the clocks constraints list.
I suggest you to check all the un-desired clocks in the constraints editor list and make sure that it is what you ment. using the output of a FF as a clock or placing logic before a clock input is usually no a good practice (async deisgn). after you will re-sync your design the "un-wanted" clocks will be removed from the constraints editor clocks list.
Tip - I'm not fimiliar with the synopsis synthisizer but in the synplify synthisizer you can view the RTL view of your design and there you can see the "clock tree" branch, if it contains un-wnated nets it could give you a good hint...
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