The warning of VCC and GND is normal in MAP file?

Hi, I am new to XILINX ISE webpack software. The map file of its "freqm" VHDL example has two warnings (see below) N77 and N78 signals. I have the following questions:

  1. This kind of warning is normal? Where to suppress it?
  2. In which file, I can see N77 and N78 net? Or, block "XST_VCC" and "XST_GND"?

I have generated the map file in its detail form, basically it is the same the warning.

Thank you very much.

Section 2 - Warnings

-------------------- WARNING:LIT:243 - Logical network N77 has no load. WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1 more times for the following (max. 5 shown): N78 To see the details of these warning messages, please use the -detail switch.

Section 3 - Informational

------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "F_INPUT_BUFGP" (output signal=F_INPUT_BUFGP), BUFGP symbol "F_PATTERN_BUFGP" (output signal=F_PATTERN_BUFGP) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary

--------------------------------- 2 block(s) removed 2 signal(s) removed

Section 5 - Removed Logic

-------------------------

The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge).

The signal "N77" is loadless and has been removed. Loadless block "XST_VCC" (ONE) removed. The signal "N78" is loadless and has been removed. Loadless block "XST_GND" (ZERO) removed.

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Another problem. When I try to run FPGA editor and Floorpanner, there is a warning from the firewall of my computer. It says it will block some functions of the two software. Is it normal? I can ignore the warning? I havn't seen any explaination on Xilinx website.

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