Xilinx ISE Bugs

No. You can only expect that if you are very careful with your simulation. Google for "HDL simulation mismatch". The simulator will execute your model. It does not check whether the model can be implemented in your target technology.

For example there are many standard cell libraries that do not have flip-flops with power on reset. Still, the synthesis tool will create a netlist without error even if your code contains initial value assignments. Then of course your model of the stimulus of the design must be accurate. And you need 100% coverage for your testbench.

Even with formal verification you can not guarantee that a correctly synthesized design will work as your simulation without putting in additional assumptions and knowledge.

Kolja Sulimma

I'd be really careful about making blanket statements about ISE problems based on postings to this forum because the original posters rarely update the thread when their problem is solved.

In particular, unexpected logic optimization is a difficult problem to track down, so it's not uncommon for a new poster to ask for help, find their error and move on. If anything, that tells me we need better messages in the map report.

Hi Mike - You allusions to the ISE being a marginal product are incorrect. IMHO it is pretty good. In past, I ran into a problem on a successive release where previous instantiation of differential driver/receivers required a change in syntax ... Found the example in docs, modified code, and off and running in 15 minutes. I have 20+ designs in last 3 years I can speak to using XST flow.

Comparing tools is a pretty personal task, and the comparison will vary depending on target design. I am a consultant, and tool expenses come out of pocket, so 20% improvement in synthesis time on a 5 minute synthesis are tough to justify. That might be different if I were designing in some of the bigger Virtex parts. Synplicity's features for incremental design, and floorplanning would be pretty attractive. I have not used the cadence tool.

Be careful with terms like "ISE bugs" though. Sometimes I find the least experienced users discover the most tool bugs.