Are there any approaches or constraints available to fix hold-time violations in the Xilinx ISE tool aimed at Virtex-2 devices? The P&R tool is supposed to automatically fix these, but if the timing results from P&R show hold violations, what is the recommended approach to eliminating them? In the ASIC world one would insert buffers in the failing path and do an incremental P&R compile - does this apply for Xilinx FPGAs as well?
Hold violations in the FPGA world generally are because the clock signal is a gated clock or generated internally in some fashion that can not be distributed with little net delay. Generally speaking this is not good design practice (at least no inside an FPGA) so the approaches are to
- Change constraints on the clock so that it is distributed with low delay (i.e. use some global clock route network).
- Change the source code to generate the clock appropriately (i.e. in a way that can be distributed via low delay).
KJ
Hi, I have an experience with Altera chip a few years ago.
Hold violation means the signal disappear too soon, that means in my opinion the related equation is too simple to hold a longer time.
I added an artificial signal: One
in the Xilinx ISE tool aimed at Virtex-2 devices? The P&R tool is supposed to automatically fix these, but if the timing results from P&R show hold violations, what is the recommended approach to eliminating them? In the ASIC world one would insert buffers in the failing path and do an incremental P&R compile - does this apply for Xilinx FPGAs as well?
Answer from Peter Alfke: In a synchronous design, you clock all flip-flops with a common clock. The Q output of one flip-flop drives (through interconnect and perhaps also other logic) the D-input of the "downstream" flip-flop. Although all flip-flops are clocked together, the clock-to-Q plus other delays assure that the "old' data is held at the downstream flip-flop input until well after the clock edge. Perfect operation!
If, however, the clock arrives at the downstream flip-flop very late, the old data may already have disappeared, and the "new" data will be clocked in, which is one form of a race condition. You never have this problem when you us the global clock distribution, for its skew is less than the propagation delay from one flip-flop to the other. But if you use local clock routing, or -heaven forbid- use clock gating or other unsavory methods, then you can (or will) create hold time problems. The solution is to "don't do that". Use an un-gated global clock, together with selective Clock Enable. Inserting extra delays in the data path is a dangerous Band-Aid method, only to be used in emergencies. Try to understand your problem first, before fixing it. Peter Alfke, Xilinx
in the Xilinx ISE tool aimed at Virtex-2 devices? The P&R tool is supposed to automatically fix these, but if the timing results from P&R show hold violations, what is the recommended approach to eliminating them? In the ASIC world one would insert buffers in the failing path and do an incremental P&R compile - does this apply for Xilinx FPGAs as well?
Answer from Peter Alfke: In a synchronous design, you clock all flip-flops with a common clock. The Q output of one flip-flop drives (through interconnect and perhaps also other logic) the D-input of the "downstream" flip-flop. Although all flip-flops are clocked together, the clock-to-Q plus other delays assure that the "old' data is held at the downstream flip-flop input until well after the clock edge. Perfect operation!
If, however, the clock arrives at the downstream flip-flop very late, the old data may already have disappeared, and the "new" data will be clocked in, which is one form of a race condition. You never have this problem when you us the global clock distribution, for its skew is less than the propagation delay from one flip-flop to the other. But if you use local clock routing, or -heaven forbid- use clock gating or other unsavory methods, then you can (or will) create hold time problems. The solution is to "don't do that". Use an un-gated global clock, together with selective Clock Enable. Inserting extra delays in the data path is a dangerous Band-Aid method, only to be used in emergencies. Try to understand your problem first, before fixing it. Peter Alfke, Xilinx
violations in the Xilinx ISE tool aimed at Virtex-2 devices? The P&R tool is supposed to automatically fix these, but if the timing results from P&R show hold violations, what is the recommended approach to eliminating them? In the ASIC world one would insert buffers in the failing path and do an incremental P&R compile - does this apply for Xilinx FPGAs as well?
Hi Peter, My situation is different from what you described.
My design was for PCI core. In PCI core, there are two global PCI signals: nIRDY, and nTRDY that drive a lot of loads and the signals cannot be latched before they are used. In Alera chip situation, nIRDY/nTRDY are not treaded as global signals and they use normal routes for all connections in a design. That causes
nTRDY signal disappear earlier than global clock signal in some flip-flops in my design, causing hold time violations. After understanding its reasons, I added a constant logic One to the related equations and delayed nTRDY signal disappearance. After adding constant One logic, the hold violations disappear.
For Xilinx chip, nIRDY/nTRDY have global net so that the hold violations don't happen.
Weng
So for individual registers, it is possible that nTRDY dissappear before
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