Hello.
I'm designing an asynchronus circuit with combinatorial loops which are strongly required for the function of the circuit. To avoid unwanted logic optimization, the gates are seperated in different components. As mapper preferences, I've UNchecked the following options:
- Trim unconnected signals
- Logic optimization across hierarchie
Synthesis works fine, translation even better, but mapping results in the following errors (some of the following kind):
ERROR:MapLib:661 - LUT2 symbol "XLXI_1/wa_vh45/inputtemp1" (output signal=XLXI_1/wa_vh45/SIGNALFELD) has input signal "input" which will be trimmed. See the trim report for details about why the input signal will become undriven.
Unused block "XLXI_1/wa_vh45/inverters_i0/inverter_i1/output1" (ROM) removed.
Xilinx Help and google-search didn't result in useful hints about MapLib:661 Looking at the RTL-Schematic, I find connections from the input to the output of the circuit, through the trimmed part of the circuit. Why does the mapper trim the needed components, and is there a possibility to keep software from thinking about the sense of the circuit and just doing what I want? The simulation with modelsim exactly does what I'm expecting.
I need this circuit for my diploma-thesis and would be very thankful for every hint to solve this problem.
Regards,
Jonas
PS: I'm using Xilinx ISE 7.1.04i