Hi, I'm working on some AES code. I've declared the values of a particual register in one of the blocks to be a constant.
[snip] 4'h0: rcon_func=32'h01_00_00_00; [snip]When synthesizing the design,the bits {23:0] are being trimmed and it's leading to cutting out a whole buncgh of mappings .essentially a useless synth output.
Any suggesteions on how to work around this latch trimming and force the ISE not to trim latches/ff? or is there a better way to declare values?
So you mean it isn't really a constant? If it is the logic should be right. If it isn't put a register off of some input pins so that you can store a value into it. A shift register will only need a few pins for all your non-contant constants.
-- glen
If your logic is being trimmed, it is because it is not doing anything. The signals either have a fixed value or are never assigned a value and remain at "unknown". When I have this problem and I can't figure out what is causing it, I run a simulation and it will show you the logic error you have made.
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
You seem to be describing a synthesis issue which is not my expertise, but I will comment on this to say that the constant register logic would not survive the mapping process either.
An important distinction to make is that this is not actually trimming behavior but optimization to a constant value. The optimization may then trigger some trimming if for example, a FF control signal no longer has any loads after a FF is optimized away. Trimming is easy to block with an "S" property, but optimization can not currently be blocked. An enhancement to the "S" property to block optimization during mapping is currently scheduled for version 8.1i, which is not so close.
Meanwhile, an easy solution to prevent the optimization is to use an INIT value for the register that is the opposite of the eventual constant value.
Bret
Oh yeah, it will also be trimmed if the logic is not used anywhere. :)
-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.