Hi all, I am trying to implement a small ALU module using the Xilinx ISE web pack and the simulator is Silos. When I try to synthesize this design, it gives me an error for the division. I have implemented division directly, i.e. out
/ is not a synthesizable operator.
Cheers, JonB
If you want division and don't have a Virtex4 (?!) you'll have to do the division yourself in hardware or in software.
Small microcontrollers have rarely had division in their ALUs with the software division supported by routines with a series of add/subtract, rotate through carry, and shift operations.
Oh yes it (sort of) is! From the Synplify reference manual:-
Operators /, mod, and rem are supported for compile-time constants or when the right argument is a power of 2.
Cheers, Symon 'Pedant' Brewer.
Compile-time constants would be something like, out
Lookup table is the answer... FPGA-based designs usually have abundant LUTs...
Kelvin
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