Does anybody know if it is possible to directly instantiate a Xilinx Fifo Generator asynchronous fifo in VHDL? I have a design that requires the use of them, and I think it would be easier to not to have to keep track of different coregen cores as opposed to just having it written into the VHDL. I've seen other xilinx cores that allow this (dds compiler, for instance) but the fifo generator user guide doesn't say anything about it.
Thanks.
Yes, and it's pretty easy.
Look at what coregen creates. You'll see a template with a bunch a parameters added.
I have been successful instantiating the template and modifying the parameters myself, without the use of coregen.
Good luck, G.
Thanks, I was in need of this information, too.
Have you done this for synthesizeable code? I'm interested in being able to synthesize the fifos. Thanks for your help.
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