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FIFO Full logix - V4

I am working with a dual port RAM FIFO module that has a 32-bit write port and an 8-bit read port using asynchronous clocks. The full and empty flags use static thresholds...meaning I didn't choose the programmable option...it uses the default setup in COREGen. There are

2048 32-bit elements in the FIFO. I am seeing the FULL flag go high after the 2046th 32-bit write. The 2047th 32-bit write is accepted by the FIFO, but the last 32-bit write causes an overflow and the data is not written into the FIFO.

So I went in the COREGen and tried to use the one-time programmable full threshold for the FULL logic and the maximum number it allowed was 2046. Does this mean that an 'X-element' FIFO is really full when X-1 elements have been written? If I need a FIFO to hold 2048 elements do I have to create one with 2049 elements? I looked in the FIFO user guide and haven't seen an exact explanation.

Thanks.

Reply to
motty
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Is it really important to have a capacity of 2048 entries? Detecting FULL in an asynchronous FIFO is a tricky procedure. It is much easier when the last position is not being used. A FIFO should really never go FULL. That is an indication of insufficient depth... Peter Alfke

Reply to
Peter Alfke

Thanks Peter. I was basically just questioning if I was seeing things correctly. It makes sense that an async FIFO would behave this way. This is a temporary FIFO that I am using and I don't even need 2048 elements but I was filling the FIFO anyways. I can just back off an element and it should be fine.

Reply to
motty

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