Hello,
I'm having a hard time fitting the two fifo's I need into my StratixI device (EPS10) because of the power of 2 requirement on the depth.
Are there any fifo variants that lift this requirement?
Right now we're instantiating 2 sc_fifo's within a AHDL file. (I need two
3600 word fifos which would fit, but have to use two 4096 word fifos which do not fit)I'm aware of the FIFO Partitioner, but would like to avoid this if possible.
Thanks, Ken
Would it be thinkable to have multiple FIFOs behind each other ? EG a 2048 & 1024 & 512 ?
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
Hi Ken,
I've done this before by writing my own fifo using the altsyncram megafunction. altsyncram has a parameter MAXIMUM_DEPTH which allows non-power-of-2 depths. Adding single-clock FIFO functionality (read and write ptr management at a minimum) shouldn't be more than 20 lines of HDL. You can go one step further and implement "stacked" memory yourself, but then you have to write the muxing yourself, which altsyncram does implicitly with MAXIMUM_DEPTH.
-- Pete
and
If you need asynchronous operation (2 clocks) you could mix both methods using a synchronous (single clock) FIFO after the async one. Of course cascading FIFO's will increase the latency.
Hi Rene,
How would this work? A little latency wouldn't hurt. Is it very tricky to stack fifo's?
Thanks, Ken
Hi Pete and Gabor,
I'm not HDL savvy enough myself, but I could handle the code if its available :) My application can stand a little latency if cascading fifo's is easy. Is this cascading easy or are there examples on the net somewhere?
One other thing is that I don't need a free solution.
Thanks, Ken
allows
(read
of
course
easy.
Cascading is fairly simple. The only thing you do extra is control data flowing between FIFO's. The first FIFO would be read whenever the second FIFO is not full and not almost full (full - 1). The almost full is required to prevent data read on one clock from writing a full FIFO on the next. Then the second FIFO is written when new data is read from the first. I haven't used Altera FIFO's but usually this is one clock cycle after reading a non-empty first fifo.
If you have independent read and write clocks, the first FIFO could be single-clock using the write clock for the second FIFO. Alternately you could make the first FIFO dual-clocked and the second FIFO single- clocked using the read clock from the first FIFO. The second approach may be easier for the almost-full flag implementation, since it is easier to produce flags in a single-clock design.
With Xilinx designs I use the COREgen FIFO's and this approach works either way.
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