Dear all:
I am working on Virtex2 Pro on Xilinx. In the design, I instantiated an asynchronous fifo from coregen. The two clock domains are entirely unrelated. Simulation sems to run fine. However, during place and route, I keep getting timing error from one clock domain to the other clock domain. I was under the impression that coregen would have implicitly decouple the two clock domains for timing. Apparently not. So, I attempted to cut off the asyn fifo from timing analysis by
INST "a/b/c/rxfifo" TIG;
which according to the manual, will ignore all timng path which passes through the instance. But it doesn't quite work. The timing violation is within the asyn fifo itself. I have even turned on the cross-clock analysis. The timing wizard says I just need to separate the signals to two timing groups.
Perhaps anyone has any insigh I imagine an asyn. fifo is so common people must have come ccross it.
help appreciated.