Xilinx EDK 6.3 : DDR Burst Mode

Does anyone uses the PLB DDR Chip on the PLB Bus of the PPC? Does anyone uses the burst modus. According to the xilinx docu the timing constraints has to be set to 2ns for the burst modus to a specific clock domain connection. I have a lot of problems when i set the bust modus and in special because i do set the

2ns in the ucf. If i set 3ns the timing is easy fullfilled.

Just to share some experiences i want to know if others do get the same problems with the DDR Chip?

Does anyone uses SDRAM an the burst modus? Are there also any problems with that burst modus?

Thanks for any feedback at all.

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