Hi
I have designed an SDRAM controller and nearly ready to synth and P&R. M question is do I need to add any offset constraints to the ucf? I see tha the Xilinx XAPP134 uses them but the newer DDR designs which are generate using MIG do not. Any info would be appreciated?
Cheers
Jon
It's important to constrain any timing that is critical to the SDRAM. Normally you can use offset constraints to require outputs to switch within a specified time of the input clock. However in a design where all of the outputs are constrained to use IOB flip-flops, there is really no room for place & route to change the timing offset, unless you're not using global clock resources. This may be why there are no offset constraints in the MIG.
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