1. Home
  2. Field-Programmable Gate Arrays
  3. DDR constraints in Xilinx/UCF, Synplicity?

DDR constraints in Xilinx/UCF, Synplicity?

HELP! How to constrain source-synchronous DDR inputs in Xilinx? In Synplify Pro?

Double Data Rate input scenario:

CLK = 500MHz (Period = 2ns, Pd/2=1ns, Pd/4=0.5ns)

Data rate = 1.0 Gb/sec (Ideal bit valid window = 1ns)

time t=0.0 1.0 2.0 3.0 4.0 etc... __________ __________ _______ CLK _________| |__________| |_________|

_____________________________________________________________ DATAi___X__________X__________X__________X__________X__________X__

_____________________________________________________________ DATAa___XXX_______XX__________XXX_______XX__________XXX_______XX__

DATAi = ideal (perfect edges, 0.5ns Tsu/Th before/after CLK edge) DATAa = actual (degraded edges, smaller valid window, less Tsu/Th)

Assume DATAa is valid 300ps before clock edge, 400ps after clock edge, for a total valid time of 700ps.

The clock does go into a DCM, and data is captured in DDR IOB flops

Assume no clock jitter either; I'm just trying to figure out the Xilinx UCF constraint syntax by example; their data books are inconsistent...

# With this: NET "CLK" TNM_NET = "CLK"; TIMESPEC "TS_CLK" = PERIOD "CLK" 2.0 ns HIGH 50.00%; NET "DATA" TNM = "DATA";

# I've tried this: TIMEGRP "DATA" OFFSET = IN: 0.3 : BEFORE CLK; TIMEGRP "DATA" OFFSET = IN: 0.4 : AFTER CLK;

# And this: TIMEGRP "DATA" OFFSET = IN: 0.3 VALID 0.7: BEFORE CLK HIGH; TIMEGRP "DATA" OFFSET = IN: 0.4 VALID 0.7: BEFORE CLK FALL;

And several other variants, but get nothing sensible (or nothing at all) out of the compiler and timing reports. Ditto for entering Synplicity scripts and asking it to pass good .ucf/ncf forward...

I'm much more accustomed to the Synopsys Design Constraints format (DesignCompiler/PrimeTime), and I'm struggling to get this thru Synplify and ISE.

Sorry if the post is premature. I didn't find much yet by googling, but wanted to get this out to the world before the weekend, since I'll since I'll be working most of it. 8-P

Thanks in advance for your help!

mj

Reply to
jjohnson
Loading thread data ...

schrieb im Newsbeitrag news: snipped-for-privacy@o13g2000cwo.googlegroups.com...

just an advice (maybe you did it already) if you are planning to use DCM at

500MHz you need speed grade -12 check out that the LX100 is available in that speedgrade in the timeframe you need it. Maybe it is, just sounds like a good idea to check out now (to avoid surprises). I would be very careful with any design that depends on the DCM output of 500MHz. 2cent advice.

well you probably could get away without using DCM also (and using slower speed grade)

and as of contrains if you make proper (R)LOCed macros then you can keep most of the design uncontstrained as the timing is guaranteed by the LOC of the primitives. sure if the router makes hassle you may even need to end up using dedicated rotuing constraints, but again thats not timing constraints

Antti

Reply to
Antti Lukats

Thanks Antti, for both replies. We've already got a board built and half-running with V4LX100-11's (ordered early, paid big bucks, got engineering samples).

We had the design running at 360MHz in a V2Pro a few months ago (DCM, source-synchronous mode, no IDELAY, plus a few LOC constraints), but I'm still not sure I got the timing constraints right. SynplifyPro doesn't seem to support hold-time constraints, and Xilinx's UCF syntax boggles my mind.

UCF doesn't seem to support multiple constraints on a port (like Synopsys does with set_input_delay -max|-min -add_delay); UCF appears to overwrite them. (Last one wins, plus some other priority rules they have...)

The 500 MHz was slightly rounded up for clarity in illustration. We need 360MHz for the current 12-bit A/D converters, and 420/480 if we move up to 14/16-bit converters.

We hope to put this in an ASIC someday, at which point I'll need complete timing constraints; it would be great if everybody supported the same constraint format (like Synopsys .SDC), or if I could find an English UCF translator...

Thanks again,

mj

Reply to
jjohnson

Hi

So what constraints did you use. We are trying to get DDR to work for virtex 4 lx160

Reply to
jitendra

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.