Debugging EDK DDR interface

Dec 17, 2007 1 Replies

Hi all,



We built a custom board with Spartan3 1200E and Quimonda 32MBx16 DDR (HYB25DC512160CF-6). The schematic is similar to Spartan3E StarterKit. Now I am trying to put the DDR to life in EDK using Microblaze 6 and OPB_DDR. Well the thing does not work from the begginig as usual. I have properly swapped all of the address lines (including bank address) and other busses to MicroBlaze endianicity.



The Xilinx Memory test works with 8 bit transfers up to 4 MB, then it fails. Other tests (32 and 16bit fails from the start).



Does anybody has any useful hints how to identify the problems (pinout, timing...) in such cases (without oscillocope if possible).



Cheers,



Ales


Try this:

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*&numgm=5&filter=0&proxystylesheet=xilinx&client=xilinx&site=EntireSite&btnG=Google+Search&output=xml_no_dtd&sort=date%3aD%3aL%3ad1&ie=UTF-8&oe=UTF-8&requiredfields=-status:archive&q=ddr+phase+shift&submit2.x=0&submit2.y=0&submit2=Search&lang2search= or search xilinx website for ddr phase shift

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