OFFSET constraints with derived clocks - Xilinx FPGA

May 18, 2006 1 Replies

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Hello, I am using Virtex2p Xilinx FPGA. My design accepts a clock input of

25Mzh. A system clock of 75Mhz is derived from 25Mhz input with a DCM. All of my internal logics are operating at this derived clock of 75Mhz. And the same clock is driven as output of the FPGA on the source synchronous interface side also. All the IO are driven from 75Mhz clock. Similarly all the inputs will be sampled at 75Mhz clock.

--- I have a problem here. How do give OFFSET_IN, OFFSET_OUT constraint for my IOs? Xilinx is not accepting internal nets in OFFSET constraints. It asks for clock input. The only clock input is 25Mhz. Since this input clock is not having any fixed phase difference with 75Mhz clock, the OFFSET values with respect to 25Mhz will not contrain the design properly.

What is the solution for this?

I did lot of googling and search on xilinx web-site, and not able to find any answers.

Any inputs would be greatly appreciated.

Thank you, Muthu

I hope you won't be annoyed that I don't directly answer your question.

You state that all inputs are sampled by the 75MHz clock. I assume then that this is using the FFs within the IOBs? If that is the case, then an offset_in is really irrelevant. There are only two possible offsets, one with the pad going through the builtin delay element to the flipflop, and one with the delay element bypassed. In both cases the offsets relative to the 75MHz clock can be found from the data sheet, and I would imagine is also in the timing report file.

Also, are all the outputs clocked? That is, they are all using the output flipflop in the IOBs? Then the same thing applies to them, except that there is no delay element and the only variable affecting the output offset is the IO standard used.

OFFSET constraints with derived clocks - Xilinx FPGA

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