Xilinx Chipscope Sample rate

The sample rate depends on the speed grade of the part, especially the block RAM timing, and how full the part already is without ChipScope. Fairly full designs cause larger routing delays. You'll have to build your design with ChipScope to see if it meets your timing specs.

The ILA-core has a clock input. The data is then sampled on the rising or falling edge (depending on how you set it up) of that clock. Usually you just pick the fastest clock signal in your design for that.

Basically yes. In ChipScope this is - at least most of the time - nothing you have to worry about, since the clocks to update the signals and to sample them are the same. The only thing you should take care of is that the sample clock is synchronous to the signals you want to analyze.

Thank you for your advice. But in the CoreGenerator I could only choose wether to use the rising or the falling edge. I could not find which clock is meant. I use a development board from Xilinx ( --> Spartan-IIE-LC). I know that a 100 MHz oscillator is used in the design. It is connected to one of the 4 global clock nets. I suppose the ILA Core uses this clock. But yet I didn't find a pull down menue or a dialog box in the GUI to choose which clock signal of the design is used for sampling the signals.

Can you tell me where to choose it?

Tobias

You assign the clock when you instantiate the ILA in your design. CoreGenerator can generate example VHDL-files for you, if you check the corresponding option. Then you can assign whatever clock you like to the "CLK"-port of the ILA core in the instantiation.

With Chipscope Pro comes a "Core Inserter" you can use. It offers a GUI to make all the signal connections, including the clock. That way, you don't have to instantiate ILA/ICON in your design.

one

menue

Ouuh yes - I see. I use the "Core Inserter". And I already connected the clock signal to a certain oscillator in my hardware. I forgot that I did it. And now I wondered why it worked. Thank you very much.

Question: Is it possible to see the clock signal also in the scope? Or ist only possible to see the Data/ and trigger signals?

Tobias

Well, you can add clock signals to the data signals you want to sample like any other signal... But since you always sample at the rising or falling edge of your clock, it will always be 1 or 0, respectively, so that's not really useful.