Chipscope Core Generator:VIO

Hi Everyone,

I have generated a VIO core using the xilinx Chipscope Pro Generator. I move my design into xilinx ISE. For some reason, when i look at my clock signals, it thinks that signals going into my VIO core are clock signals. Is this just the way the vio core works or is there something wrong?

Thanks,

Andy Wilkins

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Andy Wilkins
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