Working on a polyphase decimator and interpolator. I'm trying to use the same chunk-o-logic to implement both functions. In either case, it is easiest to drive the control logic from the fastest of the two clocks. I'm trying to figure out the most elegant way to achieve this. Any thoughts, ideas, links?
Thanks,
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Martin Euredjian
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If you can work this out, it would be the easiest:
Say you have a set of frequencies you want to handle:
{f1, f2, f3, f4...fn}
Clock your control logic at a frequency that can generate all of these other frequencies. E.g., for {2,3,5,6 whateverHz}, select your control clock to be 30 whateverHz. To clock data in or out of the decimator/interpolators, use clock enables that are synchronous to the data and the control clock but have a duration of 1 control clock.
Slightly off topic, but if you're doing this fixed point, you might have to adjust gains depending on input and output rate for consistent scaling.
if you intend to implement the filter in an FPGA, it will be a pain to have so many derived clocks. if you do partial reconfiguration, the probability of P&R trouble can be very high...
Clock enables are your friend. The processing of the samples does not have to be spaced equally in time. All that matters is that the samples are spaced equally when converting to/from analog. For example, if the sampling is at
15/16 of the filter's clock, you can disable the filter for > if you intend to implement the filter in an FPGA, it will be a pain to have
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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.
He didn't say how many frequencies he was going to use, or what kind of FPGA, or how many bits in the samples. But even if he had 20 different frequencies, you could do all in a single FPGA and use a provisioned register to select the input and output chip enable rates, as well as the frequency dedendant filter gains (if any).
A few frequencies. Not enough data yet. Samples can be up to 16 bits wide x 3 (RGB image processing). Virtex 2V1000.
Had to put the project on the shelf for a few days. I'm very tempted to run the whole thing at the highest possible frequency (in the context of what needs to be done, not the highest attainable by the FPGA) and use clock enables. It would seem to me that this is the easiest way to stay out of trouble. I like that.
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
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