sending multiple char on RS232

You don't say in what way this isn't working. You may need to wait before step 4 until the hardware is ready to accept another character (if the transmitter has no buffer). That is, you may need to wait until the first character has been transmitted.

If you need this "flow control", then the most likely behaviour without it is that only a single character is transmitted (either 'h' or a corrupted character, depending on the behaviour of the transmitter when you write a character to it when it isn't ready).

I got only only signal from the UART model saying that the transmit bus is empty(TBE) if 1 then empty. Here is what I do step by step:

1. until input arrive, then go to 1
2. read input if input = '1' then go to 3, else back to 1
3. put 'h' on the data bus, wait until TBE is 0 go to 4
4. wait until TBE = 1 then go to 5
5. put 'i' on the data bus, wait until TBE is 0 go to 6
6. wait until TBE = 1 then back to 1

it hang on step 5. wait for TBE to be 0

by the way, if i go to 1 instead 5 on step 4. It is working, and it just a normal echo program

the problem has solved by adding a extra clock cycle between 4 and 5, but I still don't understand why that will work. Maybe need to wait longer for sending the byte. If someone know, please tell me. anyway,

thanks Mike~!

BTW - In the UARTs I've used (Z8530, 16c450) the UART sets TBE to a 1 when it can accept a byte to be transmitted.

Without seeing your code it would be difficult to help you.

-Dave

Dave, sorry for late reply.

Here is the code: entity Main is Port ( btn : in std_logic_vector(3 downto 0); sel : in std_logic_vector(7 downto 0);

TXD : out std_logic := '1'; RXD : in std_logic := '1'; led : out std_logic_vector(7 downto 0); CLK : in std_logic; RST : in std_logic := '0'; ann : out std_logic_vector(3 downto 0); lcdout : out std_logic_vector(7 downto 0)); end Main;

architecture Behavioral of Main is

------------------------------------------------------------------------

-- Component Declarations

------------------------------------------------------------------------ component UARTcomponent Port ( TXD : out std_logic := '1'; RXD : in std_logic; CLK : in std_logic; --Master Clock DBIN : in std_logic_vector (7 downto 0); --Data Bus in DBOUT : out std_logic_vector (7 downto 0);--Data Bus out RDA : inout std_logic; --Read Data Available TBE : inout std_logic := '1'; --Transfer Bus Ready RD : in std_logic; --Read Strobe WR : in std_logic; --Write Strobe PE : out std_logic; --Parity Error Flag FE : out std_logic; --Frame Error Flag OE : out std_logic; --Overwrite Error Flag RST : in std_logic := '0'); --Master Reset end component;

component LCDcomponent Port ( an3 : out std_logic; an2 : out std_logic; an1 : out std_logic; an0 : out std_logic; lcddisplay : out std_logic_vector(7 downto 0); datain : in std_logic_vector(7 downto 0)); end component;

------------------------------------------------------------------------

-- Local Type Declarations

------------------------------------------------------------------------

type mainState is ( idle, receive, initSendX, sendX, waitSendX, initSendY, sendY, waitSendY);

-- type sendStates is (

-- sendX,

-- sendY,

-- sendDir,

-- sendAction,

-- sendIdle);

-- signal sendState, sendNextState : sendStates := sendIdle;

------------------------------------------------------------------------

-- Signal Declarations

------------------------------------------------------------------------ signal dbInSig : std_logic_vector(7 downto 0); signal dbOutSig: std_logic_vector(7 downto 0); signal rdaSig : std_logic; signal tbrSig : std_logic; signal rdSig : std_logic; signal wrSig : std_logic; signal peSig : std_logic; signal feSig : std_logic; signal oeSig : std_logic;

signal state : mainState := idle; signal stNext : mainState; signal X : std_logic_vector(7 downto 0) := "00110010"; signal Y : std_logic_vector(7 downto 0) := "00110100"; signal direction: std_logic_vector(2 downto 0) := "110"; signal action : std_logic_vector(1 downto 0) := "11";

signal UARTReady : std_logic := '0'; signal clock : std_logic := '0'; signal reset : std_logic := '0'; signal dataReady : std_logic := '0';

shared variable send : std_logic := '0';

------------------------------------------------------------------------

-- Module Implementation

------------------------------------------------------------------------

begin

LCD: LCDcomponent port map ( an3 => ann(3), an2 => ann(2), an1 => ann(1), an0 => ann(0), lcddisplay => lcdout, datain => dbOutSig);

UART: Uartcomponent port map ( TXD => TXD, RXD => RXD, CLK => CLK, DBIN => dbInSig, DBOUT=> dbOutSig, RDA => rdaSig, TBE => tbrSig, RD => rdSig, WR => wrSig, PE => peSig, FE => feSig, OE => oeSig, RST => RST);

SET_DATA: process(btn, sel) begin if btn(0) = '1' then --reset reset

the sendY state should be when sendY =>

UARTready

YiQi;

I got only only signal from the UART model saying that the transmit bus is empty(TBE) if 1 then empty. Here is what I do step by step:

1. until input arrive, then go to 1
2. read input if input = '1' then go to 3, else back to 1
3. put 'h' on the data bus, wait until TBE is 0 go to 4
4. wait until TBE = 1 then go to 5
5. put 'i' on the data bus, wait until TBE is 0 go to 6
6. wait until TBE = 1 then back to 1 it hang 1) If the UART received a char (RDA = '1') then goto 2, else goto 1

2) Read the char from the UART. If the char is ASCII '1' (31h) then goto 3 else goto 1 ( rdSig

Thanks Dave. Yes, you were correct

sorry that i have serval version of this code now, and i even comfuse myself. as a result, my program is not accroding to the steps.

For rdSig and wrSig, I am reading and writeing at the same time, but I just ignore the incoming data while i am sending it. Since serial port using 2 different bus, it should be ok, and it shouldn't effect the outgoing data.

Let me know if my assumption is wrong.

The send signal is for a process(not shown here) to inform this main process the X and Y is has change and ready to send it out, that's why my program start with sending.

Besides these, what are the possiblity that the simulation works correctly, and after the the design flow, the actual on-chip running becomes wired? How could I have the simulation close enough to the on-chip running

Thanks for your advice and help, YiQi