VHDL: Address Decoder

it's the best method. Also I am not sure why there are four 4:1 muxes in the design.

Yes. Get a better text editor. Need to eliminate the tabs and add a few line feeds.

-- Mike Treseler

sure it's the best method. Also I am not sure why there are four 4:1 muxes in the design.

I agree. If you're gonna code like that, you might as well use Verilog. Cheers, Syms.

Sorry about the format. I cut and paste from ISE into Xilinx's forum web site. Looks like it butchered the code.

JTW

New Listing---

entity Decoder is

Generic ( ASIZE : integer := 32; BSIZE : integer := 12);

Port ( clk : in std_logic; rst : in std_logic; address : in std_logic_vector(ASIZE-1 downto 0); reset_stb : out std_logic; reg1_stb : out std_logic; reg2_stb : out std_logic; reg3_stb : out std_logic; valid : out std_logic); end Decoder;

architecture Behavioral of Decoder is

constant PMC_ADDR : std_logic_vector := X"00008"; constant RESET_ADDR : std_logic_vector := X"000"; constant REG1_ADDR : std_logic_vector := X"004"; constant REG2_ADDR : std_logic_vector := X"008"; constant REG3_ADDR : std_logic_vector := X"00C";

begin

process (clk, rst) begin if rst = '1' then valid

Yo there,

Me think if you close the if statement, you should be able to remove the 4 to 1 Mux...

if (address(ASIZE-1 downto BSIZE) = PMC_ADDR) then valid