Dual Port RAM Block RAM using Core Generaot

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Hello

I'm using the core generator from Xilinx for installing a true dual port RAM But I wonder how I can handle it in the VHDL code ??? Could someone give me an advice??

This is what Iknow already: Of course I put a component in the archticture (as I did it in the example below)

architecture Behavioral of dpram is component dpram port ( addra: IN std_logic_VECTOR(8 downto 0); addrb: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); dinb: INOUT std_logic_VECTOR(15 downto 0); douta: OUT std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(15 downto 0); ena: IN std_logic; enb: IN std_logic; wea: IN std_logic; web: IN std_logic ); end component;

begin

This is a dual port ram, then you have 2 ports... (duh!) port a and b. in port a you have: addra: IN std_logic_VECTOR(8 downto 0); clka: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); douta: OUT std_logic_VECTOR(7 downto 0); ena: IN std_logic; wea: IN std_logic;

Where: addra: is the address where you will store the data. clka: is the clk dina: is the data that will be store in the ram on address addra douta: is the data stored in address addra ena: enable the ram wea: write the data DINA in address ADDRA, if asserted, else, read the data in address ADDRA and put in DOUTA

If you want write in RAM, you will assert WEA, put the address in ADDRA, and the data in DINA, all in one clock. If you want read, you will put the adrees in ADDRA, and read in DOUTA.

Something this...

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