Hello
I'm using the core generator from Xilinx for installing a true dual port RAM But I wonder how I can handle it in the VHDL code ??? Could someone give me an advice??
This is what Iknow already: Of course I put a component in the archticture (as I did it in the example below)
architecture Behavioral of dpram is component dpram port ( addra: IN std_logic_VECTOR(8 downto 0); addrb: IN std_logic_VECTOR(7 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); dinb: INOUT std_logic_VECTOR(15 downto 0); douta: OUT std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(15 downto 0); ena: IN std_logic; enb: IN std_logic; wea: IN std_logic; web: IN std_logic ); end component;
begin