virtex4 software reset problem.

HI

I made a small amendment to a tutorial I found online "

Please see my C code area with asterisk to find the problem. I am guessing the problem is with software reset. If yes, How do I fix this?

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

entity multiplier is port( clk : in std_logic; rst : in std_logic; a : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); p : out std_logic_vector(31 downto 0) ); end multiplier;

architecture IMP of multiplier is

begin process (clk, rst) begin if(rst = '1') then p