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Using both Verilog and VHDL for Xilinx simulation

Hi,

How do I setup synopsys_sim.setup for simulating both Verilog and VHDL using VCS for a Xilinx FPGA?

I need for instance have SIMPRIM point to both the VHDL and the Verilog compiled library path, I did try using a : and simply append them but it failed.

/michael

Reply to
Michael
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have you tried using "vlog" to compile verilog codes and "vcom" to compile VHDL codes?

Reply to
Jack Leong

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