Xilinx WebPack 8.2.03i: can't make .bit file when memories used in design

I can:

-make (and use succesfully) .bit files under Xilinx WebPack 8.2.03i

*unless* the design contains RAM- whether I specify it in Verilog, or use CoreGen to specify it.

I can:

-use Verilog-defined memories if I compile under Synplify Pro, bring the resulting file into WebPack and place,route, and generate .bit file there.

I can't:

-use memories under WebPack- place and route is OK, but "Generate Programming File" fails with no error messages. This happens under XP Pro and WIn2000.

What am I doing wrong?

-- Per ardua ad nauseam