Problem with PINs XC3S700A-4FG484

In the quick start tutorial, it says connect DIRECTION with PIN K13 (SW7 signal on board), but after browsing through ug300.pdf and s3a schematics, I don't see anything that remotely makes sense. I understand I need a input signal, but I have no idea which PIN would give me that on S3A board.

Here is my vhdl source: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity counter is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end counter;

architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin

process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int

Reply to
Fei Liu
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Did you mean ug130.pdf instead of ug300.pdf? If so, K13 pin on the FPGA chip is connected to the switch SW7. This means that you need to assign your DIRECTION input to K13 in your constraints file (edit ucf file).

Dan

Reply to
jkljljklk

Yes, you have to control the switches and pushbuttons on the board manually.

Reply to
jkljljklk

I see, many thanks. I guess I can use either of the manual switch to control DIRECTION. One thing I don't understand is that the clock is

50MHz and my timing constraints is only a few macro seconds. I wonder how I can control DIRECTION that fast by manually pushing the switch.

Fei

Reply to
Fei Liu

That constraint doesn't mean that you will be switching at that rate, it only defines the maximum rate.

Reply to
jkljljklk

I now understand that the vhdl source was doing a up and down counter depending on the direction switch. So I have properly set up PINs: NET "CLOCK" TNM_NET = CLOCK; TIMESPEC TS_CLOCK = PERIOD "CLOCK" 40 ns; OFFSET = IN 10 ns BEFORE "CLOCK"; OFFSET = OUT 10 ns AFTER "CLOCK"; NET "COUNT_OUT" LOC = R20; LED0 NET "COUNT_OUT" LOC = T19; LED1 NET "COUNT_OUT" LOC = U20; LED2 NET "COUNT_OUT" LOC = U19; LED3 NET "DIRECTION" LOC = V8; SW0 NET "CLOCK" LOC = E12; GCLK5 50MHz

E12 is GCLK5, the 50MHz oscillator on S3A chip. What's confusing me here is that if period is 40ns, wouldn't frequency be 25MHz? It'd make sense period is 20ns. I am using the numbers in Fig 12 in qst.pdf.

After I load impact and program the board, the first 4 LEDs are lit, while the remaining 4 unlit. V8 is the pin for SW0 next to LED 0. After It's a slider switch, turning it high or low makes no difference. The leds don't blink... It's almost as if the clock source is not driving the logic.

Fei

Reply to
Fei Liu

The clock source is driving the logic. The LEDs are blinking too fast for the human eye to tell the difference. Add a counter circuit to divide the clk frequency down to something the human eye can visually verify the blink rate and watch it count up and down.

Reply to
Dwayne Dilbeck

I slowed down the clock by 1000,000 using another counter, now I can see the LEDs blinking. Very nice, thanks!

Fei

Reply to
Fei Liu

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