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Modular Design in WebPack

Design consists of two modules: VHDL top-module and EDIF-netlist instance. In other words, the design is broken down into two files and I need to assemble it. Usually, simulation tools allow for geterogeneous sources. Simulators comile source files to extract design units and put them into libraries. Do sinthesis tools favor this practice?

EDIF-module's design is a cell named SCH1 located in SCH1_LIB library. It has two inputs I1, I2 and output O. How should parent VHDL module look like?

Development System Reference Guide at

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states that Modular Design is an option of Xilinx Development System. Does WebPack support it?

Is Modular Design the only solution?

How to allocate floorplan area automatically?

How do you simulate modular designs?

Thanks.

Reply to
valentin tihomirov
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What you are trying to do as far as I can tell is not a modular design in sense of Xilinx tools. You simply have mixed sources. There is more than one way to do this under ISE (I believe Webpack is the same). I can't remember the proper way off the top of my head, but one way is to create a normal VHDL-flow design and then set Macro Search path in Translate options to where you have your edif file.This assumes that the top level is VHDL.

/Mikhail

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MM

Have a look at our current TechiTips

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. Method2 is relevant to want you want to do.

Modular design is an add-on to ISE have a look here

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. It is aimed mainly at team design and may not be what you want.

John Adair Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.

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John Adair

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