Design consists of two modules: VHDL top-module and EDIF-netlist instance. In other words, the design is broken down into two files and I need to assemble it. Usually, simulation tools allow for geterogeneous sources. Simulators comile source files to extract design units and put them into libraries. Do sinthesis tools favor this practice?
EDIF-module's design is a cell named SCH1 located in SCH1_LIB library. It has two inputs I1, I2 and output O. How should parent VHDL module look like?
Development System Reference Guide at
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