Hi all,
I've been going over the structure of the Virtex CLBs and something has me a little confused. The LUTs/function generators appear to have no clock, so I assume they act a normal logic gates. That is, inputs F/G are "processed" immediately and glitches are possible as with any array of logic gates.
If there is no clock, why are there setup and hold time specifications (relative to the clk) for the F and G inputs?? If there was to be a setup time for a slice I would have thought it would be defined with repsect to the output flip flop - something like
delay through LUT + setup of output FF
however flip flop and LUT setup times are listed seperately.
Any clarification will be much appreciated.
Klod