Hi All,
I'm developing a system which will work in the irradiated area. One of the components is the triple redundant register with asynchronous loading from the control bus. Additionally the register's should be refreshed with the system clock. The control bus is asynchronous.
My implementation uses the asynchronous Clear and Preset to implement the asynchronous loading, while Data input is used for synchronous refresh of the register's contents.
The implementation (of single bit) for Xilinx is shown below:
======================== XILINX IMPLEMENTATION =========================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work;
entity tripsigas is port ( input : in std_logic; output : out std_logic; init : in std_logic; -- State after reset awe : in std_logic; -- asynchronous loading arst : in std_logic; -- aynchronous resets, prevent -- optimizing out redundant FFs rst : in std_logic_vector(2 downto 0); -- synchronous resets clk : in std_logic );
end tripsigas;
architecture tripsig1 of tripsigas is type my_data is array(2 downto 0) of std_logic; signal d : my_data; signal fclr,fset, s_output : std_logic; signal din : my_data; component FDCP generic ( INIT : bit := '1'); port ( Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC; PRE : in STD_ULOGIC ); end component;
begin -- trip1 fclr din(j1), -- Data input PRE => fset -- Asynchronous set input ); din(j1)