How much (I would like to know only the order of magnitude) static current does a configured XC3S200-4TQ144C device need with clock disabled, all IO tristated etc.? A microamp? ;-)
Best regards Piotr Wyderski
-- "If you were plowing a field, which would you rather use? Two strong oxen or 1024 chickens?" -- Seymour Cray
It's in the data sheet.
It's not small. Thin oxides leak. Very think oxides leak like a sieve.
Think milliamps rather than microamps.
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Is it that "quiescent current" parameter?
If the above is correct, it means "Typical 10, Maximum 80 mA", holy Molly! So there will be no battery sustaining of the RAM memory contents, not good. :-(
Best regards Piotr Wyderski
-- "If you were plowing a field, which would you rather use? Two strong oxen or 1024 chickens?" -- Seymour Cray
The data sheet says 120 mA (Iccint + Iccaux + Iccio), and that is not a typo... If you need very low quiescent current, then pick a CoolRunner CPLD (very low current, but very limited complexity compared to XC3S200) or use older technology, previous generation devices. All 130 nm, and especially 90 nm devices have considerable quiescent current, even though Xilinx uses some circuit "tricks" to keep the current down. Part of the leakage is through the ultra-thin gate dielectric, part is through transistors that are not perfectly turned off (sub-threshold leakage). It's the price you pay for high performance and high density (small size, low cost). This is perhaps the most frustrating aspect of the newer technology...
Peter Alfke, Xilinx (from home) Merry Christmas to all !
Yes, unfortunately my device is quite complex, so no CPLD chip can be used instead of an ol' good FPGA technology. I wanted to store some data inside the chip for several weeks when the main power supply is off, but in this situation a separate FRAM memory will be used. BTW, since I am very new to the Xilinx world and its nomenclature, how should I interpret the "CLB" term? The manual says that
"The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing synchronous as well as combinatorial circuits. Each CLB comprises four interconnected slices"
and I presume that "slice" means something comparable to Altera's "Logical Element" (assumption based on figure 6 in ds099.pdf). So why there is a separate name for a group of slices, i.e. where should I count used CLBs instead of slices?
The performance is really very impressive and the price is very low (~25 USD per chip including taxes @ 1 chip quantity), which makes that Spartan a perfect chip for my hobbyist purposes. Unfortunately, nothing above 3S200-144 is easily available, but the same is with Cyclones. Playing with FPGAs is a rare hobby. :-(
Eh... :-(
Thank you, Merry Christmas to you too! :-)
Best regards Piotr Wyderski
-- "If you were plowing a field, which would you rather use? Two strong oxen or 1024 chickens?" -- Seymour Cray
Hello, Piotr (nice name, if I may say so) Xilinx and Altera implement logic mainly in 4-input look-up tables with an associated flip-flop. We call that a Logic Cell. Two of the neighboring Logic Cells share some connections, so we call that a Slice, and either 2 or 4 Slices are grouped together in a CLB. For estimating purposes, stay with the LUT = Logic Cell = the number of flip-flops. Slices and CLBs are not very meaningful for estimates, although some people like them. Sorry to disappoint you about the leakage current... Peter Alfke
How big is the low power end of the FPGA market? Does it need high speed?
I'm not a silicon wizard. I think it was common to do a die-shrink on existing designs and move them to a new fab line. You don't take full advantage of the new line, but you get some/much of the benefit without much engineering time.
Is it feasable to go in the other direction? Can you take a current design and (roughly) make all the rectangles bigger and then run it on an old fab line with low leakage? You would have to figure out how fast it goes, but you wouldn't have to do much engineering on either the chip design or the tools.
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Hal, many things can be done. But the outcome would be circuits that are slower and bigger = more expensive. Some users would gladly pay the price and accept the slower performance, for the low-power benefit. But how big is that market? Presently, the main manufacturers do not think it's worthwhile. This is Capitalism 101, which seems to work, and has given you superb circuits at a low price. If low current is so important, demonstrate it with your pocketbook... And don't forget, you can still buy the low-current circuits introduced almost 10 years ago. Peter Alfke
I meant: "demonstrate it with your wallet". English as a second language, especially during holidays... Peter
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