Hello,
I know this topic is beaten to death but I am a bit unlcear some things.
I've recently encountered metastability issues that caused my FPGA to do unpredictable things. Someone suggested that I synchronize my inputs to the clock domain and that seemed to solve the issue. Googling this topic showed that a two stage Flip Flop is sufficient to increase MTBF for metastability. My question is do I need to do this for all input signals? How would one do this with a design containing 30 to 40 input signals? Which types of inputs can I get away with not using two stage FF?
So in the sample code below, both INA or INB can change state while the clk is transitioning and this could lead to metastability. Synchronizing INA and INB would help, but what about INC and IND?
Would the experts just synchronize everything and forget about it?
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-- Sample code with asynchronous inputs
----------------------------------------------------------------------------------------- entity blackbox is port ( Clk : in std_logic; RST : in std_logic; INA : in std_logic; INB : in std_logic; INC : in std_logic; IND : in std_logic; Out : out std_logic ); end blackbox;
architecture Behavioral of blackboxis begin
BB: process(Clk, RST) is begin
if(RST = '1') then Out