Synplify warning CL209

Hello,

When synthezing the design with Synplify Pro 8.0 it gave the follwoing Warning.

CL209 Input port bit of spi_addrs(4 downto 0) is unsed. CL209 Input port bit of spi_addrs(4 downto 0) is unsed. CL209 Input port bit of spi_addrs(4 downto 0) is unsed. CL209 Input port bit of spi_addrs(4 downto 0) is unsed.

I am sure that I am using the slice (4 downto 1) as an input to the mux.

I tried by assigning this slice to an intermediate wire (signal) and then to the mux input . But again it is giving the same error.

Following is the relevant piece of code.... ntity Ctrl_Ram is port( Ctrl_Data_In : in WORD; Ctrl_Addrs : in unsigned(3 downto 0); Spi_Addrs : in unsigned(4 downto 0); Ctrl_Wr : in std_logic;

Intl_Rst : in std_logic; Clk : in std_logic;

Reset : in std_logic;

Data32_Out : out DWORD; Data16_Out : out WORD ); end entity Ctrl_Ram;

Architecture arch of Ctrl_Ram is begin spi_addrs_intl Addrs_In Addrs_In Addrs_In 'X'); end case; end process Addrs_Mux;

Thank you.

-- Mohammed A Khader.