Hello,
I am toying around with some GLUE logic to interface a 1655 to an ISA bus. I have added my code below, however, when I try to synthesis the code I recieve the following error:
"IRQ[0]" at isagluesimp,vhd (55) because is does not hold its value outside the clock edge
I recieve that for all the IRQ lines in the IRQ vector. This error goes away when I comment out the:
ELSIF (BCLK'EVENT AND BCLK='1' AND AEN='0' AND SA=address1 AND FLAG= '0') THEN
line. ( I surrounded it in stars so it is more readable.
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
------------------------------------ ENTITY gluesimp IS
PORT( SA: IN STD_LOGIC_VECTOR (19 downto
0); --system address lines D: INOUT STD_LOGIC_VECTOR (7 downto 0); --data bus IRQ: OUT STD_LOGIC_VECTOR (10 downto 0); --IRQ vector. Only one pin is used depending on the IRQ selected
IO16: OUT STD_LOGIC; --when addressed, IO16# is asserted RSET: IN STD_LOGIC; --when asserted, system has reset, all values return to initial state IOR: IN STD_LOGIC; --when asserted, the system is doing an IO Read IOW: IN STD_LOGIC; --when asserted, the system is doing an IO Write BCLK: IN STD_LOGIC; --bus clock from CPU board (8.33MHz) used as clk signal AEN: IN STD_LOGIC; --when asserted, address is invalid (DMA read in progress)
----------UART SIGNALS--------------------------------------
ADD: OUT STD_LOGIC_VECTOR (2 downto 0); --A2, A1, A0 used to select internal register of 1655 CHIPSEL: OUT STD_LOGIC; --CSA, CSB, CSC, CSD chipselect for 4 different channels (ACTIVE LOW) DATA: INOUT STD_LOGIC_VECTOR (7 downto 0); --Data register for both input and output to/from card ISR: IN STD_LOGIC; --Interrupts from the 4 channels. These will be anded together RD: OUT STD_LOGIC; --Read strobe WR: OUT STD_LOGIC; --Write strobe RESET: OUT STD_LOGIC); --Reset --INTN: OUT STD_LOGIC; --Configurable depending on the type of interrupts used (MAY NOT BE USED) --TXRDY: IN STD_LOGIC; --If TX FIFO buffer is full, this will be set (ACTIVE LOW, MAY NOT BE USED) --RXRDY: IN STD_LOGIC); --If RX FIFO buffer is full, this will be set (ACTIVE LOW, MAY NOT BE USED)
END gluesimp;
------------------------------------
ARCHITECTURE behavior OF gluesimp IS
CONSTANT address1: STD_LOGIC_VECTOR (19 downto 0) := X"002E8";
--declare base address vector for channel CONSTANT interrupt: STD_LOGIC_VECTOR (10 downto 0) := "00000000001";
--declare interupt vector SIGNAL FLAG: STD_LOGIC; --used to inform the internal system an interrupt has been thrown SIGNAL TRUEADDRESS: STD_LOGIC_VECTOR (11 downto 0); --contains the usable address SIGNAL TRUEDATA: STD_LOGIC_VECTOR (7 downto 0); --contains the usable data SIGNAL TEMP: STD_LOGIC_VECTOR (2 downto 0); --address sent to the UART
BEGIN
PROCESS (BCLK, RSET, ISR) BEGIN FLAG