VHDL and Latch

Hi John, Thank you for your suggestion.

Silicon is living and money to me.

Weng

Hi KJ, I have another question for you.

1. Is any combinational equation with target signal in both right part and left part of the equation a latch like your equations 3 or 4 show?

1. Is there any general algorithm to change such an equation to a latch equation?

Thank you.

Weng

Weng

A latch is the most benign form. There are oscillators (however when they occur by accident, they are not necessarily this obvious): Q

While Jim and Peter can debate whether or not it's a latch or an oscillator, suffice it to say that any time you have something of the form of equations #3 and #4 where you have the same signal on both sides of the '

Not sure what you mean....all four forms that I presented are exactly equivalent 'latch equations', they will produce the same synthesized result. Equations #1 and #2 involve less typing then #3 and #4.

Also keep in mind, that latches do not need to fit into a single equation, any time that you form a combinatorial loop you have to be concerned about how this will get implemented. A combinatorial loop happens when you have multiple equations, none of which inherently shows any feedback but taken together the whole set does. A simple example of this would be

#5 Q

Peter, No argument from me as you seem to be saying the same thing I said.

I interpreted Weng's question as being, when a combinational signal is on both the right and left side of an equation, is the only hardware solution a latch.

The answer which we both observed is no and the simple case is an oscillator.

Cheers, Jim

Hi KJ, Jim and Peter, Thank you for your response and help.

Anyway now I understand the latch a little more than before the posting.

In coding experiences, when writing code equations, a reasonalble FPGA engineer will never generate a situation that leads to a signal appearing in both sides of logic equation in concurrent area. Because most of time the odd behavior equations would be fully beyond the acknowledgable. And there is no reason to generate an oscillator neither.

Jim correctly repeated my question and both of you gave me a right answer.

Weng

Weng, > 2. Is there any general algorithm to change such an > equation to a latch equation? I have not seen any evidence of one you can expect different tool vendors to support.

For RTL code, if you want a synthesis tool to reliably create a latch library part, only use #1 or #2 (below from KJs post). Going further, if you want to avoid portability issues with some of the ASIC synthesis tools, then use only #1.

Hi Jim, I am not going to write an odd equation to confuse VHDL compilers that would be stupid, but just wondering about how can a VHDL compiler figure out its inherent complex structures.

The best way to do FPGA design is to follow rules. No exceptions.

standard VHDL form, how to use a new possible attribute to let VHDL compiler to generate an error information, instead of a warning information, and the last and not the least, how to avoid confusing VHDL compiler by using a signal name in both side of "

So, just making sure I understand this. The synthesis tool may or may not choose to generate a "latch inference" warning, depending on whether a latch is natively supported by the target device.

And the reason for this warning is that it is not possible to reliably implement a latch, unless the target device has built-in support for it.

Is the above correct?

-Michael.

That is pretty much it.

If you look at Xilinx's FPGA datasheet, most families' slice FFs have an FF/latch configuration bit, which I presume (I do not remember trying to infer latches on FPGAs) means slice FFs can be configured as latches. The problem then becomes one of generating a suitable latch enable pulse. To prevent disorderly feedback (as you would in a latch-based counter) while the latches are enabled, this enable pulse needs to be very short and will be problematic on FPGAs since FPGAs are not particularly good at generating, distributing (on anything other than clock nets) and handling sub-nanosecond signals.

You are better off sticking with FFs in FPGAs/CPLDs and even ASICs (unless extreme power and area conservation are primary preoccupations) unless you have very specific/unusual reasons to do otherwise - in programmable logic, the whole FF is there and using power either way.

In news: snipped-for-privacy@h3g2000cwc.googlegroups.com timestamped 8 Mar 2007 14:16:15 -0800, "KJ" posted: "[..]

[..] [..] suffice it to say that any time you have something of the form of equations #3 and #4 where you have the same signal on both sides of the '

Someone made such a not particularly unique claim in this thread as: "[..]

[..] Latches are only half as big as flipflops [..] [..]"

A latch is a type of flip-flop.

Most definitely, yes.

No-one was calling the *circuit* combinational; it's the

*loop* that Kevin was so describing. In doing so he was conforming to long-established usage in the synthesis community for the description of any cycle in the network that is not broken by an explicit storage element.

Of course, if you concern yourself with asynchronous state machines of any kind then you expect to deal with such cycles and you no longer speak of "combinational" circuits. But in the purely synchronous world of mainstream design, every storage element should have its synchronous inputs fed by the output of a purely combinational circuit. In such a context it is neither unreasonable nor ambiguous to use "combinational loop" to describe a specific and pernicious kind of design error.

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Please desist from nitpicking. Ralf's meaning was entirely self-evident. Common usage being what it is, when describing any kind of bistable element (not "flip-flop" please) that is *not* an edge-triggered D-type flip-flop, it is necessary to qualify the phrase "flip-flop" with something such as "S-R flip-flop".

There is a tiresomely large lexicon of names for the different flavours of bistable element:

bistable multivibrator flip-flop latch register Eccles-Jordan relay

Save for the last one, I can easily find examples of multiple and overlapping meanings of all these. To disambiguate them we must rely either on tiresome and wordy qualification of each usage, or intelligent inference from context.

Only the most irritatingly pedantic would insist on such blindness to context as your comment exhibits.

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Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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If something is 'combinatorial' it does not imply anything about how it is used (i.e. whether or not the output is fed back to one of the inputs).

As far as whether this combinatorial feedback gets used or not in designs...absolutely. Depending on just what you're designing you're either very aware of it or it is something happening behind the scenes. To the person designing the flip flops that go into the FPGA, you bet that they are very aware of the combinatorial feedback loop that they are in fact designing and it's characteristics. To the person writing code that will eventually get downloaded into that exact same FPGA, probably not...even though they should be aware of this (from the standpoint of avoiding ever creating such a thing in their own designs).

Kevin Jennings

[..]

No-one was calling the *circuit* combinational; it's the

*loop* that Kevin was so describing. In doing so he was conforming to long-established usage in the synthesis community for the description of any cycle in the network that is not broken by an explicit storage element. [..]"

Thanks for the information.