Latch/flip flip without the use of process

Hi,
I should have probably sent this question to the VHDL newsgrp but since it
has low activity, I've decided to send it here.
It is well documented that processes should be used to code sequential syst
ems. The texbook gives an example of a D latch/flip flip. With FPGA tools,
i have to use a process so the tool makes use of the available on-chip flip
flops. But i wonder what if I describe a D latch and flip flop without the
use of process:
e.g.
1- latch: Q
Reply to
Karl
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t has low activity, I've decided to send it here.
stems. The texbook gives an example of a D latch/flip flip. With FPGA tools , i have to use a process so the tool makes use of the available on-chip fl ip flops. But i wonder what if I describe a D latch and flip flop without t he use of process:
#1 will work as a latch; #2 will work as a flip flop. Both lines of code w ill be triggered upon any change on either D or Clk. But just because the code gets triggered and executed does not imply that Q gets updated. #1 wi ll only update if Clk=1; #2 will only update when rising_edge(Clk) is tru e. At any other time there is no update to Q simply because there is no 'e lse ...' clause (which there shouldn't be for either a latch or flip flop).
The code is fine, your apparent desire to use a latch in an FPGA design wil l cause you problems if you implement.
Kevin Jennings
Reply to
KJ
From what you wrote, the issue you fail to understand is that every concurrent statement is a process. That is why they are concurrent, each concurrent statement runs as a separate process. In fact, what makes a process statement a process is that it is a concurrent statement. What the process statement does is to tell the tool to stop treating the following lines as processes, rather treat them as sequential statements within the current process.
So why do you not want to use a process statement to define a FF?
To answer your question, as KJ wrote, each of your examples define a type of register. When a signal level is used as the trigger it defines a latch. When a signal edge is used as the trigger it defines an edge sensitive FF. Seems rather obvious, no?
--

Rick C
Reply to
rickman
Thank you KJ and Rickman for your answers. I wanted to confirm that the cod es are correct because in the notes I am reading it stated that flip flops /latches are coded in VHDL using a process...given your answer, it is one w ay to do it but not the only one
Reply to
Karl

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