I'm working on a quadrature decoder to interface with a rotation sensor. My thought was to have an asynchronous process that operates on the A and B signals, and then have the 'state' variable synchronous with the clock in a seperate process. The following vhdl works as expected in one simulation tool, but produces garbage when I use Quartus.
begin process(A_in, B_in) begin state(3)
Hiya,
The way you have written this code will make sure that Modelsim only 'schedules' the process if A_in or B_in changes. In a synthesized design, a process is always dependant on all its inputs, so also its internal state - er - register (which you don't have here).
If you synthesize this with Quartus (or any synthesis tool for that matter) you will get warnings that state(1) and state(0) should also be on the sensitivity list. The synthesis tool will subsequently simply generate a wire between state(1) and state(3) and one between state(0) and state(2)
What you should do here is work synchronously, something like
process(clk) signal tA, tB : std_logic; begin if rising_edge(clk) then if (A_in /= tA) or (B_in /= tb) then tA
Thanks for the reply. I incorporated the component into a synchronous process and it works fine now. However, I still have a few questions just so I can get a better understanding of what was going on.
That was my intention. I wanted the output to change *only* when one of the two inputs changed. I see what you mean that the 'internal states' were not counted as inputs though. So, how would you go about making this component so that it will change state only when the input changes?
In fact, Quartus gives the following message: "Design top_quadrature_decoder: Netlist extraction and synthesis were successful. 0 errors, 0 warnings"
Is this just a personal preference? or is there a reason one should avoid the /= operator?
thanks, Phillip
Hi Phillip,
VHDL was initially designed as a simulation laguage based on ADA using concurrent processes and the lot. Using the sensitivity list you could pick which set of events could trigger scheduling of one such process during simulation.
The 'synthesizable subset' of VHDL, be it the 1987, 1993 or 200x version, has the requirement that a process by nature is sensitive to any signal or port to the right of an ' top_quadrature_decoder: Netlist extraction and synthesis were
I think you should get a warning that something else should be on the sensitivity list as well. I'll give it a try on monday and file an SR if I don't get one.
A bit only has values '0' and '1', so saying "if x /= '0'" basically means "if x = '1'", so no problem there. However, a std_logic has seven possible values, so saying "if x /= '0'" basically means "if x='1' or x='Z' or x='H' or x='L' or x='X' or x='U'". Most of these don't make sense during synthesis and ar happily ignored, but I've had two cases where such a comparison was made on a signal that was part of a tri-state bus somewhere upstream, and the 'Z' (or tri-state) case was taken into account as well, causing a lot of initialy inexplicable behavior.
Best regards,
Ben
by the way, thanks for the info, I appreciate it.
-Phillip
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