XST 5 input mux synthesis question

Hi all,

2 questions. I am designing a 5 input mux with the following verilog

assign muxOut = (selectA) ? inputA : (selectB) ? inputB : (selectC) ? inputC : (selectD) ? inputD : E;

will xilinx know to put a 5 input mux there? How do i know if it did?

If I know that E is the latest arriving input is there a way to insure that XST puts it in the fastest path of the mux? Is there a fastest path in a 5 input mux?

Thanks

Matt

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Matthew E Rosenthal
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Matthew E Rosenthal

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