Verilog code to Physical layout?

Is there some way I can generate a physical layout (using Cadence) of a design written in Verilog and synthesized using Synopsys design compiler. I heard there was provision in Cadence for this.. Any one tried this before?

Reply to
KaRtiK
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Yes, Cadence provides tools for th entire full custom/std. cell chip design flow.

But I'll bet neither one of us (as an individual)can afford them !

Also look at Magma, they have a single tool solution ...

Cheers, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores ->

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Reply to
Rudolf Usselmann

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