Hello,
I want to compare two designs, one of which is written in verilog while the other one is in vhdl. the testcases are also written in verilog. while running the vhdl design, (using XST VHDL) .. the design compiles without error, but i couldnt figure out a way to generate the simulation netlist in verilog for the design. does there exist any such switch using which i can generate a verilog simulation netlist for designs compiled with XST VHDL
thanks in advance.,
regards Varun Jindal.