Synthesize verilog code with Icarus for Spartan?

Hello,

I need to synthesize a verilog code for a Spartan device and was wondering whether I can use Icarus Verilog for this.

I looked on the Icarus web page and it says that Icarus supports synthesis. I am pretty new to logic design and especially synthesis.

Now I try to figure out how to synthesize my code for the Spartan. There are not really any device specific options given. The compiler can just be called with the -tfpga option.

Is that all there is? Does this create me an edif file that I can import into ISE to do the place and route?

I also tried searching the gEDA list archives for answers, but could not reach the server.

Thanks for the help.

Guenter

Reply to
Guenter Dannoritzer
Loading thread data ...

"man iverilog-fpga" should give you some more answers. You specify relatively generic families and it will do synthesis for that, and generate and EDIF file. You will still need the Xilinx back-end tools to do the final map and par.

I have to admit that you will probably find that the synthesis code generator can stand for some work. Not all cases are covered yet. I would have to say that this is more for experts who are willing to poke around the tools.

If you are a software person trying to reform and go hardware, then I think you will find that the code fpga code generator source is well organized for easy update. It's also the most fun part of the Icarus Verilog source tree, as you can directly see the results of your labors in FPGAEditor:-)

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
 Click to see the full signature
Reply to
Stephen Williams

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.