XST: How to select the architecture for synthesis?

Hi,

I have an VHDL toplevel entity with multiple architectures. If I try to synthesis this with the Xilinx ISE 6.3i and the XST Synthesis Tool, then only the last architecture will be synthesized.

Therefore my question: Is it possible to select the architecture that will be synthesized and how this work?

Best Regards Mathias

Reply to
Mathias Schmalisch
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In principle you can do that in VHDL using the configuration specification like

for all : xxx use entity yyy(rtl)

..but my experience is that very few of synthesis programs support it. At least Synopsys Design Compiler doesn't. I don't know a better solution except that just to comment out other architectures and leave just one. If anyone knows a better way, let me know.

Reply to
Tuukka Toivonen

Hi,

any particular reason why you do have several architectures within your entity?

Usually as you have already mentioned the last architecture gets synthesized. You might check the XST manuals or the Xilinx homepage if pragmas might help.

According to the constraints guide for ise6.3i p. 821 xst can handle translate_on and translate_off. The constraints guide is downloadable as zipped pdf from the XILINX homepage

HTH

Ansgar

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Reply to
Ansgar Bambynek

I'm not so sure, but you can try to use the "configuration" in both your modules and top level HDL, for example:

(in module)

architecture A of Module is begin ... end A;

architecture B of Module is begin ... end B

configuration CFG_A of Module is for A end for; end CGF_A;

configuration CFG_B of Module is for B end for; end CGF_B;

(in top-level)

architecture C of TOP is ... U_Module: Module port map( ..... ); ... end C;

configuration CFG_TOP of TOP is for C for U_module: Module use configuration A work.CFG_A (for example) end for; end for; end CFG_TOP;

I hope it's not so far from the solution, bye!

Andrea

Reply to
Andrea

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