Unsupported feature error:access type is not supported

Apr 09, 2004 1 Replies

hello; i m trying to run this vhdl code for reading .cmd file...while i m trying to compile the code on the altera's max plusII software(student software),it is showing error File d:\maxw\code\93vhdllib\std\textio.vhd:Unsupported feature error:access type is not supported in d drive, i m not installing that software, i have this software installed in c drive..... can somebody can help me in this matter....please reply soon.....



-- -------------------------------------



-- Reads std_logic values from a file



-- -------------------------------------



library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use std.textio.all; use work.txt_util.all;


entity FILE_READ is generic ( stim_file: string := "sim.cmd" ); port( CLK : in std_logic; RST : in std_logic; Y : out std_logic_vector(4 downto 0); EOG : out std_logic ); end FILE_READ;


-- I/O Dictionary



--



-- Inputs:



--



-- CLK: new cell needed



-- RST: reset signal, wait with reading till reset seq complete



--



-- Outputs:



--



-- Y: Output vector



-- EOG: End Of Generation, all lines have been read from the file



-- architecture read_from_file of FILE_READ is file stimulus: TEXT open read_mode is stim_file;


begin


-- read data and control information from a file



receive_data: process



variable l: line; variable s: string(y'range); begin



EOG


The Altera Simulator doesn't support file IO. Its quite basic in that I don't believe you can give it a stimulus file either. All you can give it is a waveform, all you can get is a waveform.

You might want to consider downloading the free Xilinx Simulator. It doesn't know about LPM's but if you stick to VHDL code you get all the features of a real VHDL simulator. And a simulation without timings on any FPGA is the same.

Simon

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