The included code is used to search a serial stream for a sync word and then set a data valid flag for the sync word and the next four words in the stream. Simulation works fine but the post-place and route simulation fails to set the data valid flag. I am assuming that this is a timing problem in detecting the sync pattern but not sure how to correct it.
In addition ISE generates three warnings that I am not sure how to resolve.
If anyone has the time to look this code over and offer suggestions?
Thanks, Joel
---Code library IEEE; use IEEE.STD_LOGIC_1164.ALL;
entity downlink is
generic ( SR_WIDTH : integer := 8 );
Port ( rst : in std_logic; sio_clk : in std_logic; sio_data : in std_logic; data_valid : out std_logic; sio_word : out std_logic_vector(SR_WIDTH-1 downto 0)); end downlink;
architecture RTL of downlink is
constant SYNC_WORD : std_logic_vector(7 downto 0) := X"D5";
type t_SioState is ( SYNC, LOAD );
signal s_sio_word : std_logic_vector(SR_WIDTH-1 downto 0); signal s_data_valid : std_logic;
begin
process ( sio_clk, rst )
variable bit_count : integer range 0 to 8; variable word_count : integer range 0 to 4;
variable SioState : t_SioState;
variable v_sio_word : std_logic_vector(SR_WIDTH-1 downto 0); variable v_data_valid : std_logic;
begin
if ( rst = '1' ) then
SioState := SYNC;
v_sio_word := ( others => '0'); v_data_valid := '0';
bit_count := 0; word_count := 0;
elsif ( falling_edge( sio_clk )) then
v_sio_word := v_sio_word(SR_WIDTH-2 downto 0) & sio_data; v_data_valid := '0';
case SioState is
when SYNC =>
if ( v_sio_word = SYNC_WORD ) then
v_data_valid := '1'; SioState := LOAD;
end if;
when LOAD =>
bit_count := bit_count + 1;
if ( bit_count = 8 ) then
v_data_valid := '1'; bit_count := 0;
word_count := word_count + 1;
if (word_count = 4 ) then
word_count := 0; SioState := SYNC;
end if;
end if;
end case;
s_sio_word sio_data, data_valid => data_valid, sio_word => sio_word );
-- sys_clk