I have an async signal, call it TRIG, inside a Zynq 7020.
At the rising edge of TRIG, I want to make an async one-shot. It will leave the chip as RX and reset some outboard ecl logic. Anything from, say, 2 ns to 10 ns width would work.
The board is built, and we can't easily add more connections to the FPGA or hack in glue logic. Well, it would be ugly.
Here are some ideas:
We could play with i/o cell slew rates and drive strengths to tune the timing. And use as many delay stages (circuit B) as we like... there are tons of unused balls.
Or maybe use some internal delay path, if we can find one that is reasonably repeatable.
The compiler will probably let us do circuit A or B without whining much, but might object to the third one.
I grew up on async hairball logic, so this seems reasonable to me, but my FPGA guys are horrified. We don't want to spin up a 250 MHz PLL here and do it synchronously, for various reasons.
An internal passive pullup resistor charging an i/o pin capacitance would be fun, but I don't think we could make a short enough blip.
Any other ideas or comments?