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Spartan 2 xc2s150

Hi! I have to redesign a TTL based design of discere components into an FPGA. I have selected spartan 2 xc2s150. I have a few queries regarding the board design.

1) I want my Inputs to be 5V tolerant..which input standard should i use...LVTTL or PCI_5V ? How to select any of these standards as both require VCCO=3.3V and No Vref or VTT...?

2)If any of my xc2s150 ouput pin is an open collector, can i pull it up externally by 5V through a resistor?

3)I am intending to use a Level shifter IC(3.3V to 5V) at some FPGA outputs..is it OK to do so?

4)I dont have a global set/reset in the design, can it create problems at startup?

5)What should i do of un-used pins of FPGA...can i keep them unconnected?

Thanks for everyone's support.

Reply to
rider
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rider wrote: : Hi! : I have to redesign a TTL based design of discere components into an : FPGA. I have selected spartan 2 xc2s150. I have a few queries : regarding the board design.

: 1) I want my Inputs to be 5V tolerant..which input standard should i : use...LVTTL or PCI_5V ? How to select any of these standards as both : require VCCO=3.3V and No Vref or VTT...?

LVTTL

: 2)If any of my xc2s150 ouput pin is an open collector, can i pull it : up externally by 5V through a resistor?

Yes.

For speed reasons, use it as tri-state totem pole. First pull it up internally, then switch to tristate to activate the 5V pull-up resistor. There's a Xilinx appnote out there about that.

: 3)I am intending to use a Level shifter IC(3.3V to 5V) at some FPGA : outputs..is it OK to do so?

If 2) isn't enough, you can do so.

: 4)I dont have a global set/reset in the design, can it create problems : at startup? You don't need to use it, if you don't need the functionality

: 5)What should i do of un-used pins of FPGA...can i keep them : unconnected?

Define them as inputs with the "keeper" attribute, leave them unconected. That will make reuse easier.

: Thanks for everyone's support.

You're welcome

--
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Reply to
Uwe Bonnes

Thanks Uwe! I am using the JTAG-Master Serial Mode for FPGA configuration(Platform Flash). However i want to keep an other programming option. Can you suggest me some third party PROM which is DIP(so that i can program it with my HI-LO ALL 11 programmer)and is compatible to XC2S150 (i.e. supports the Master serial mode with appropriate pins?). I would be grateful.

Rider

Reply to
rider

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