Hi
A SoC done with EDK 6.1 using OPB_DDR core works OK in XPS but when the SoC is used in ISE flow the Xilinx OPB_DDR doesnt pass translate stage with error that asyn_fifo edif can not be loaded due to pin name mismatch!
how to make it work? there should be some fix, but can not find in Xilinx answer database at least!
thanks!
Antti
Can you check that the ddr_v1_00_b_virtex2_async_fifo.edn file is located in the /implementation directory?
I think problem is when you do an export-to-projnav flow, XPS has location pointers to all your wrapper NGC files, but not the BBD specified netlists. So if you run projnav in a directory other than /implementation, you won't pick up the BBD netlists. It's just a matter of moving ddr_v1_00_b_virtex2_async_fifo.edn to directory where you kick-off ngdbuild.
This is fixed in EDK.6.2i.
Antti Lukats wrote:
Thanks!!!!
it was so simple !!
Antti
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