Hi
A SoC done with EDK 6.1 using OPB_DDR core works OK in XPS but when the SoC is used in ISE flow the Xilinx OPB_DDR doesnt pass translate stage with error that asyn_fifo edif can not be loaded due to pin name mismatch!
how to make it work? there should be some fix, but can not find in Xilinx answer database at least!
thanks!
Antti