I'm very new to working with Xilinx tools so I may be overlooking something obvious. I'm able to synthesize with XST and simulate using Modelsim without any problems. But I am unable to implement my design because a Coregen ROM generates errors in the translate step. The ERROR messages don't seem to be indicative of the problem. I've tried referring to the Xilinx online help but it has been most unhelpful. Has anyone run into these ERRORS before?
1) ERROR:NgdBuild:76 - File "c:\xilinx\rtc2/ro256x8pre.ngc" cannot be merged into block "rom0_rom0" (TYPE="ro256x8pre") because one or more pins on the block, including pin "CLK", were not found in the file. Please make sure that all pins on the instantiated component match pins in the lower-level design block (irrespective of case). If there are bussed pins on this block, make sure that the upper-level and lower-level netlists use the same bus-naming convention.The Xilinx Answer Record #14848 says to change the bus delimiter style of the synthesis tool to match the bus macro style. But they already agree, so I shouldn't have to change anything. Also, I've made sure that all port names match.
2) ERROR:NgdBuild:604 - logical block 'rom0_rom0' with type 'ro256x8pre' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'ro256x8pre' is not supported in target 'virtex2'.This one has me at a loss. These files are auto-generated by Coregen so it leaves very little room (or so I thought) for me to screw things up. Any help would be greatly appreciated.
thanks, Jon