Using Xilinx ISE 6.1i, FPGA Editor, it is possible to edit different aspects of the design implementation directly in the .ncd-file after finishing P&R.
Say you have a huge design, that takes forever to run P&R on, is it then possible to make small changes in the .ncd-file, using the FPGA Editor, and then either generate programming files or create a simulation model of it, without running P&R first?
The changes I'm talking about, is moving pin-locations, moving components between slices and last but not least, editing PULLUP/PULLDOWN on pins. I know I can do this in the .ucf og .pcf files, but then I will definately need to rerun P&R, and I want to avoid that.
I trid to introduce PULLDOWN on a pin in a test design just now, and after I did that, I generated a new Post P&R sim model, and ran Modelsim. But nothing happened.
Then I noticed that the file I was actually editing when I had double clicked "View/Edit Routed Design (FPGA Editor)" under the "Place & Route" node in Xilinx Project Navigator was the map_.ncd file, and not the .ncd. So I trid to open the .ncd directly from FPGA Editor, and did the changes there. When I then generated the new Post P&R sim model, I got this warning:
WARNING:Anno:13 - The .ncd is out of sync (not logically equivalent) with the .ngm; therefore, an .nga will be created from the .ncd.
I have tried to find out what this actually means, but I'm new to this, so I haven't figured it out yet. Anyway, when I then started the post P&R simulation with Modelsim, the PULLDOWN was in effect.
When I tried to generate programming files, I could do that wihtout any warnings. But since I havent actually downloaded my code to an FPGA, and meassured the voltage on the actual pin, I'm not really sure weather my modification works or not.
If anyone has had experience with doing this kind of modifications without rerunning P&R, I'd like to hear about it. But any comments are welcome :-)
Sincerely
-Fred