pullup on inputs

Didn't you just ask this question in comp.lang.vhdl?

There are a number of ways:

1. Get a better version of the software, which will allow you to use fpga_editor to view the configuration of the pin.
2. Use ngd2vhdl (or whatever) to generate a human readable version of the chip contents. I *think* that this will include the pullup if it's there.
3. Download the bitstream into an fpga and measure the electrical characteristics on a curve tracer, multimeter, or whatever test equipment comes to hand.

Allan.

In your constraint file (.ucf) add the following lines to add pull-up:

################################################################################ ## PULLUP DESCRIPTION (IF NEEDED) ################################################################################ NET your_netname PULLUP;

It works well !

Laurent

______________________________________________ Amontec provides new low cost solutions for FPGA Download and Processor Debug

Hi,

In your constraint file (.ucf) add the following lines to add pull-up:

################################################################################ ## PULLUP DESCRIPTION (IF NEEDED) ################################################################################ NET your_netname PULLUP;

It works well !

Laurent

______________________________________________ Amontec provides new low cost solutions for FPGA Download and Processor Debug

If your syntax does work, you can see the pullup in the FPGA Editor for your Placed & Routed design. Find one of the IOBs, double click on the IOB and you'll get a pop-up for just that cell. Included are checkboxes for some of the IOB options including logic standard, fast/slow, and pullup. If the pullup isn't indicated *there* it isn't in your finalized design.

What is "FPGA Editor"? I tried with Floorplanner ("View/Edit Placed Design") but if I double click the iob no pupup is opened. Which tool I need to use?

thanks

Xilinx ISE - the not-free version of the tools - has the FPGA Editor, listed inter the "Place & Route" section of the design implementation as "View/Edit Routed Desing (FPGA Editor)."

I hear WebPack doesn't have this tool which gives the low-level visibility an engineer might want in order to understand how the tools are implementing the design.

The "Pad Report" is the third item on my Place & Route list. Double-clicking there produced a file that's ready to import to a spreadsheet. It's not terribly readable in the ISE window (includes delimiters, not spaces) but does include Pullup/PullDown information.

your

and

some of

The map report is the easiest place to verify that you've gotten your pullups. It has a section like this. Look under Resistor.

+---------------------------------------------------------------------------

---------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Strength | Rate | | | Delay |

+---------------------------------------------------------------------------

---------------------------------------------+ | diff_clk_out | DIFFM | OUTPUT | LVPECL_33 | | | OUTDDR | | | | diffclk_in | DIFFM | INPUT | LVDS_33 | | | | | | | clk_in | IOB | INPUT | LVTTL | | | | | | | led | IOB | OUTPUT | LVTTL |

12 | SLOW | | | | | led | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | led_b | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | led_b | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | | push1 | IOB | INPUT | LVTTL | | | | PULLUP | | | reset_n | IOB | INPUT | LVTTL | | | | | | | uled | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +---------------------------------------------------------------------------